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[VHDL-FPGA-Verilog] fifo_01

Description: 8位相等比较器，比较8位数是否相等 -- 8-bit Identity Comparator -- uses 1993 std VHDL -- download from www.pld.com.cn & www.fpga.com.cn-eight other phase comparators, Comparing the same whether the median 8-- 8-bit Identity Comparator-- uses 1993 std VHDL-- download from www.pld.com.cn
Platform: | Size: 1024 | Author: 罗兰 | Hits:

[VHDL-FPGA-Verilog] my_ramlib_06

Description: 包括各种类型存储器的VHDL描述，如FIFO，双口RAM等 -including various types of memory VHDL description, such as FIFO, Dual Port RAM, etc.
Platform: | Size: 615424 | Author: ruan | Hits:

[VHDL-FPGA-Verilog] VHDL_Memory_Library_Code

Description: 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
Platform: | Size: 23552 | Author: Jawen | Hits:

[Other] FIFO_Memory

Description: VHDL设计——FIFO存储器设计-VHDL design-- FIFO design
Platform: | Size: 7168 | Author: 钱伟康 | Hits:

[MPI] fifo_vhd_131

Description: fifo vhdl源程序-fifo vhdl source
Platform: | Size: 15360 | Author: zlw | Hits:

[VHDL-FPGA-Verilog] ram

Description: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Platform: | Size: 2048 | Author: nick | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 异步FIFO控制器的Verilog设计与实现-Asynchronous FIFO controller Verilog Design and Implementation
Platform: | Size: 5120 | Author: 陈晨 | Hits:

[Other] buffervhdl

Description: 电子EDA,VHDL语言设计8位的fifo数据缓冲器的vhdl源程序-E-EDA, VHDL language design 8-bit data buffer fifo VHDL source code
Platform: | Size: 1024 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] 8_8_FIFO_VHDL

Description: 这是关于VHDL的8*8FIFO源代码，欢迎大家下载使用-This is about 8* 8FIFO The VHDL source code, welcomed everyone to download use
Platform: | Size: 1024 | Author: 张三 | Hits:

[VHDL-FPGA-Verilog] ethernet_vhdl

Description: 千兆以太网控制器.可以调整FIFO,和传输速率,在码流层进行控制.-Gigabit Ethernet controller. Can adjust FIFO, and the transmission rate, in the code stream control layer.
Platform: | Size: 30720 | Author: 王晶 | Hits:

[Embeded-SCM Develop] fifov1

Description: FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。本FIFO的实现是利用 双口RAM 和读写地址产生模块来实现的.FIFO的接口信号包括异步的写时钟（wr_clk）和读时钟（rd_clk）、 与写时钟同步的写有效（wren）和写数据（wr_data） 、与读时钟同步的读有效（rden）和读数据（rd_data） 为了实现正确的读写和避免FIFO的上溢或下溢，给出与读时钟和写时钟分别同步的FIFO的空标志（empty）和 满标志（full）以禁止读写操作。-FIFO (FIFO queue) is usually used for data caching and asynchronous signal used to accommodate the frequency or phase differences. The realization of this FIFO is to use dual-port RAM and to read and write address generator module achieved. FIFO interface signals, including asynchronous write clock (wr_clk) and read clock (rd_clk), and write effectively write clock synchronization (wren) and write data (wr_data), clock synchronization and time effective reading (rden) and read data (rd_data) in order to realize the right to read and write and to avoid FIFO overflow or the underflow, is given with the time clock and write clock synchronization FIFO respectively empty signs (empty) and full logo (full) to prohibit the read and write operations.
Platform: | Size: 378880 | Author: lsg | Hits:

[VHDL-FPGA-Verilog] ramlib_06

Description: 这是一个有关FIFO的VHDL 程序。。。请大家下载分享。-This is a FIFO of the VHDL program. . . Please download the U.S. share.
Platform: | Size: 577536 | Author: 张亚伟 | Hits:

[VHDL-FPGA-Verilog] fifo_VHDL

Description: FIFO的源代码，详细描述FIFO的工作原理和过程，用VHDL编写。-FIFO of the source code, a detailed description of the work of FIFO principle and process of preparation with VHDL.
Platform: | Size: 9216 | Author: 胡志敏 | Hits:

[VHDL-FPGA-Verilog] video_fifo

Description: 有关视频方面的fifo设计,vhdl编写-Fifo on the video aspects of the design, vhdl prepared
Platform: | Size: 2048 | Author: 曾工 | Hits:

[Software Engineering] Asyn_FIFO_Design

Description: 异步FIFO设计的说明文档，需要注意的问题以及源码（在文中有）。是标准的异步FIFO，可综合。-Asynchronous FIFO design documentation, as well as the need to pay attention to source code (in the text have). Is a standard asynchronous FIFO, can be integrated.
Platform: | Size: 228352 | Author: 刘强 | Hits:

[VHDL-FPGA-Verilog] 16×4bitFIFO

Description: 16×4bit的FIFO设计,VHDL语言编的的，能在ISE上仿真出来结果。-16 × 4bit the FIFO design, VHDL language series that can come out in the ISE on the simulation results.
Platform: | Size: 4096 | Author: 张军 | Hits:

[VHDL-FPGA-Verilog] sram

Description: FPGA向SRAM中写入数据(VHDL编程)，包含通用fifo，sram等-FPGA to the SRAM write data (VHDL programming), contains general fifo, sram, etc.
Platform: | Size: 270336 | Author: 王刚 | Hits:

[OS Develop] FIFO

Description: 一个异步的FIFO的VERILOG程序,有测试程序-An asynchronous FIFO in Verilog procedures, test procedures have
Platform: | Size: 4096 | Author: 陈强 | Hits:

[VHDL-FPGA-Verilog] VHDL-ram_fifo

Description: VHDL的ram和fifo model code 包含众多的厂家-VHDL the ram and fifo model code contains a large number of manufacturers
Platform: | Size: 1678336 | Author: SL | Hits:

[VHDL-FPGA-Verilog] asyn_FIFOrealizedbyVHDL

Description: 一个比较经典的用VHDL实现的FIFO论文-Instance, the birthday of power wilt lift stamp cavity using VHDL wife of mother
Platform: | Size: 53248 | Author: Roger | Hits:
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